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基于CNN的多核芯片低功耗验证系统设计
Design of multi-core chip low power verification system based on CNN
【摘要】 针对目前设计的多核芯片低功耗验证系统验证过程损失较大、验证精度较低等问题,基于CNN设计了一种新的多核芯片低功耗验证系统。通过微处理器、写缓冲器、程序存储器和SDRAM中断控制器组成硬件结构。微处理器外部连接3个接口,通过静态设计降低功耗,写缓冲器对数据进行替换。采用单片机在上电复位时利用SDRAM中断控制器控制系统电路。引入CNN技术,通过集中度验证、低功耗特征重现、验证系统建立完成系统软件操作。实验结果表明,基于CNN的多核芯片低功耗验证系统可将验证过程损失降低10%,精度提高15%。
【Abstract】 Aiming at the problems of large loss of verification process and low verification accuracy of the currently designed multi-core chip low-power verification system,a new multi-core chip low power verification system is designed based on CNN. The hardware structure is composed of microprocessor,write buffer,program memory and SDRAM interrupt controller.The microprocessor is externally connected with three interfaces to reduce power consumption through static design,and the write buffer replaces the data.The SDRAM interrupt controller is used to control the system circuit when the single chip microcomputer is powered on and reset.CNN technology is introduced to complete the system software operation through concentration verification,low power feature reproduction and verification system establishment.The experimental results show that the multi-core chip low power verification system based on CNN can effectively reduce the loss of verification process by 10% and improve the accuracy by 15%.
【Key words】 CNN; multi-core chip; low power verification; verification system; microprocessor;
- 【文献出处】 电子设计工程 ,Electronic Design Engineering , 编辑部邮箱 ,2023年22期
- 【分类号】TP332;TN40
- 【下载频次】25