【作者】 张永伟；

【导师】 王晓蕾；

【作者基本信息】 合肥工业大学 ， 微电子学与固体电子学， 2015， 硕士

【摘要】 高精度、低功耗模数转换器是当今的研究热点之一。在高精度模数转换方面,Sigma Delta模数转换器,在众多类型的ADC中脱颖而出,由于其采用过采样技术、噪声整形技术以及数字抽取滤波器,大大降低了对模拟电路设计的要求,同时实现了其它ADC无法达到的精度。但是也要看到,由于采用过采样技术,Sigma DeltaADC的所能达到的带宽有限,很难兼顾速度和精度。本文围绕Sigma Delta ADC中调制器部分(另一主要部分为数字抽取滤波器)开展研究与设计。首先采用Matlab Simulink工具进行了系统建模和仿真,充分考虑非理想因素对调制器系统性能的影响,包括运放的有限直流增益、有限带宽和压摆率、积分器输出摆幅、时钟抖动、采样电路热噪声等,对各非理想因素进行量化分析,为后续电路设计提供了设计依据。深入分析了非理想效应对调制器性能的影响。通过分析各结构的优缺点,结合项目设计指标,本文所设计Sigma Delta调制器最终采用三阶单环一位量化开关电容结构,结合系数优化,实现了高精度的设计要求。本文重点设计了第一级积分器,在调制器的第一级输入端加入了两个小电容,与采样电路构成一阶模拟低通滤波器,对进入调制器的信号带宽加以限制；在时序设计方面,采用了下极板采样技术,结合全差分电路的优势,大大减小了开关非理想效应对系统性能的影响；加入了斩波稳定电路,有效的降低了系统的噪声基底,抑制了低频噪声及系统失调,提高了调制器的动态范围。并详细讨论了电容最小值的取值,在减小开关电容采样电路热噪声的前提下,减小了芯片面积和功耗开支。采用Global Foundry 0.35um CMOS工艺,完成了本文提出的三阶单环一位量化调制器的电路设计。电源电压3.3V,过采样率为512,输入信号频率为73.8Hz,信噪比达到127dB,有效位数可以达到20bits,功耗为3.94mW,符合设计指标要求,满足高精度低功耗的应用需求。更多还原

【Abstract】 High-precision, low-power ADC is one of the hot spots of research nowadays. In the area of high-precision ADC, sigma delta ADC stands out in many type of ADCs. Due to the use of techniques such as oversampling, noise shaping and digital decimation filter, it has reduced the requirements for analog circuit design greatly and achieved the precision that other ADCs cannot. However, bandwidth of sigma delta ADC is limited also due to the use of oversampling technique, so there is a difficult balance between speed and precision. This paper focuses on the part of modulator of sigma delta ADC (the other part is digital decimation filter) to conduct research and design.First, we use tools of MATLAB and Simulink to do system modeling and simulation, so as to fully consider the influence on performance of the modulator system that non-ideal factors make, which includes limited op-amp DC gain, limited bandwidth and slew rate, the integrator output swing, clock jitter, sample circuits thermal noise and so on. Quantitative analysis of the non-ideal factors is helpful for designing the following circuits.By analyzing the advantages and disadvantages of the structure, combined with the project indicator, the structure of sigma delta modulator designed in this paper eventually uses the structure of third-order, single loop, one-bit quantization with switched capacitors, combined with the coefficient optimization to meet the design requirement of high precision. This paper focuses on the first-stage integrator, two small capacitors are added to input end of the first-stage modulator, combined with sampling capacitors, to compose a first-order, low-pass analog filter, so bandwidth of the signals which enter the modulator is limited. In terms of time sequence design, technique of bottom plate sampling is used, combined with the advantages of fully differential circuit, which has greatly reduced the influence of non-ideal switching effect on system performance. Besides, chopper stabilization circuit is added, which has effectively reduced the noise of basement, suppressed low-frequency noise and offset of the system and improved the dynamic range of the modulator. And minimum value of the capacitance is discussed in detail, on the premise of reducing thermal noise of the switching capacitance sampling circuit, area and power consumption of the chip is reduced.Using the Global Foundry 0.35um CMOS process, this paper has completed design of the proposed modulator circuit, which is third-order, single-loop and one-bit quantization. Under power supply voltage of 3.3V, sampling rate of 512 and input signal frequency of 73.8Hz, SNR is 127dB and ENOB is up to be 20 bits, power consumption is 3.94mW, which meets the design requirements and satisfy the application requirement of high precision and low power consumption.更多还原