【作者】 马娜娜；

【导师】 徐宁；

【作者基本信息】 武汉理工大学 ， 电路与系统， 2014， 硕士

【摘要】 随着集成电路快速地发展，模拟电路和数模混合电路在片上系统（System-on-Chips）的比例越来越高。然而，由于复杂的模拟电路设计约束，模拟电路设计自动化技术并没有像数字电路设计自动化技术那样迅速地发展。模拟电路设计自动化已经成为整个片上系统设计流程中的瓶颈。在模拟电路设计自动化过程中，最重要的两个步骤是布局和布线。在数字电路中，布局结果很大程度上影响了接下来的布线质量。对于模拟电路而言，由于布线不允许走在已布的器件上，布局结果对接下来的布线过程影响会更大。在数字电路中，运用拥挤度评估方法指导布局优化过程。对于模拟布局过程而言，由于电路尺寸更小，使得更为准确的评估变成可能，比如布通率的评估。本文设计和实现了一种基于隐式连接图的模拟电路布线器，实现了模拟电路自动化布线。提出了布通率评估模型，指导模拟电路布局优化过程。本文的主要工作如下：一、设计和实现了一个模拟电路无网格布线器系统。该布线器系统基于隐式连接图布线模型，采用A*启发式算法进行路径搜索。首先，通过最小生成树算法把多端线网拆分为一系列的两端线网；其次，扩展障碍块边界线，延长扩展线直到与布线区域边界相交，得到隐式连接图；再次，在布线图上用A*启发式算法搜索线网路径。最后，用GTK语言实现了布线结果的可视化。实验结果表明，用该模拟电路布线器系统，线网的布通率达到99%以上。二、提出了针对模拟电路的布通率评估模型。该布通率评估模型的创新点如下：1）评估了布线需求和障碍需求，用权值定量地预估了布线区域的拥挤度情况；2）采用动态模型布线算法预测线网可能的布线路径。和“L”型、“Z”型模型布线方法相比，算法以拥挤度值最小为导向，探索了多于两个拐点的布线模型，非常高效和准确地预测线网的布线路径，更加符合实际布线器的布线路径；3）提出了水平垂直扩展算法和角扩展算法对Bounding-Box进行扩展，在扩展的Boundig-Box里面，运用DPR算法预测线网的可能路径。根据预测的布线路径拥挤度情况，判断路径是否能够布通，从而求出布局结果的布通率。实验表明，该模型能够正确地评估布通率。更多还原

【Abstract】 With the rapid development of integrated circuits, analog and mixed signalcircuits is gaining more portions in system on chips. However, due to the complexityof design constraints, analog circuits’s design automation technology has notdeveloped as quickly as for digital circuits. Thus, analog circuits design automationhas become the bottleneck for the whole design flow of SoCs. Placement and routingare the two most important steps in the design automation process.In digital circuits,placement solution has great impact on the following routing quality. In analogcircuits,routing is not allowed on top of the placed active devices.The placementsolution has even more impact on the following routing process.In digital circuits,congestion estimation methods are performed to guide the placement optimizationprocess. For analog placement process, due to the smaller circuit size, more accurateestimation, i.e., routability estimation, is possible.A gridless router system be designed and implemented in this thesis.The systemis based on the implicit-connection graph and solve the problem of analog automaticrouting. This thesis presents routability estimation model to guide the analogplacement optimization process. The main contributions are as follows:A gridless router system is designed and implemented. The router is based on theimplicit connection graph. A*heuristic algorithm be used for searching routingpath. Firstly，multipin nets are decomposed into several two-pin subnets by usingthe minimum spanning tree algorithm.Secondly, The implicit connection graph isconstructed by extending the borderlines of each obstacle to routingboundaries.Again,A*heuristic algorithm is adopted to search the path of subnetsin the routing map.Finally,the result of routing become visualization by usingGTK language.Experiment shows that the completion rate of routing reach99%and above.Aroutability estimation model for analog circuits is proposed. The innovations ofthe model are as follows:1)The routing demand and obstacles demand areestimated.A weights quantitatively estimate the congestion of routing area.2) Adynamic pattern routing (DPR) algorithm is adopted to predict the possiblerouting path of subnets. Compared with L-shape or Z-shape Pattern routing algorithm, this approach can explore patterns with more than two bends underminimal congestion aware.The algorithm is more efficient and accurate.Theapproach predict subnets’s the possible routing path,which in line with therouting path of the actual router.3) The horizontal/vertical expansion algorithmand angle expansion algorithm are proposed. The DPR algorithm search thepossible routing path of subnets in the expanded Bounding-Box. According to thecongestion weights determine whether the subnet can be routed.Then, theroutability of the placement solution be obtained.Experiment shows that thismodel accurately estimate the routability.更多还原