【作者】 李经章；

【导师】 张玲；

【作者基本信息】 重庆大学 ， 信号与信息处理， 2012， 硕士

【摘要】 PCI Express(PCIE)总线作为第三代IO总线技术，因其具有传输带宽高、全新的点点互连架构和对PCI总线高度兼容等优点已在计算机平台中获得广泛应用。为充分发挥PCIE总线的优点，推广PCIE总线在嵌入式系统等场合的应用，本文设计了一款基于FPGA的PCIE数据传输系统，为应用PCIE进行数据传输提供了一种新的低成本方案。本文在对PCIE协议深入研究的基础上，采用自顶向下的设计思想，对PCIE数据传输系统进行顶层设计和模块划分，根据PCIE IP接口完成PCIE数据传输系统应用层的RTL级描述、仿真及验证，分析了其仿真和验证结果，并对系统进行实际测试。论文主要包括以下几方面的内容：首先，对PCIE协议规范进行全面详细的研究，在透彻理解PCIE协议的基础上，分析PCIE纯粹端点设备的实现条件，选定系统开发平台，按照自顶向下的设计思想，对PCIE数据传输系统进行顶层设计和模块划分。其次，利用Quartus II工具对PCIE IP进行例化并分析IP接口，采用Verilog HDL对所划分的PCIE IP配置模块、PCIE应用层辅助模块、PCIE应用层核心模块进行RTL级设计。其中PCIE IP实现了PCIE协议功能，通过64位Avalon-ST接口和应用层进行数据通信；PCIE IP配置模块实现了PCIE IP配置信号采集功能和通过LMI接口配置PCIE配置空间错误报告能力寄存器功能；PCIE应用层辅助模块实现了接收端口转换、发送端口转换、接收数据缓冲和MSI缓冲功能；应用层核心模块实现了Rc_slave和链式DMA数据传输功能。论文在DMA基础上实现了链式DMA功能，减少了数据传输对CPU资源的占用，大大提高了传输效率。最后，对所设计的PCIE数据传输系统整体进行仿真测试。搭建仿真测试平台，对系统整体进行功能仿真，将综合适配后的电路下载到FPGA中进行时序验证，在PC机上利用软件对系统进行实际测试，并对相关仿真测试结果进行分析。基于FPGA的PCIE数据传输系统的仿真和测试结果表明，系统各模块逻辑功能均达到设计要求，PCIE数据传输系统可通过Rc_slave和链式DMA两种模式和PC机主存储器交换数据，DMA读速度达173MB/S，DMA写速度达207MB/S。本设计为利用低成本FPGA实现PCIE数据传输提供有效可行的实现方案，推广了PCIE总线的应用范围，具有很好的应用前景。更多还原

【Abstract】 As the third generation IO bus technology, PCI Express(PCIE) has a lot advantagesuch as high transmission bandwidth, new interconnect architecture, highly compliablefor PCI bus,etc and so been widely used in computer platform. In order to give full playto the advantages of PCIE bus, promote PCIE bus to be applied in embedded system,this article designes a PCIE data transmission system based on FPGA, provides a newlow cost solution for PCIE data transmission.This article employs the idea of top-down design to conduct the top-level design ofPCIE data transmission system and module division on the basis of in-depth studiesabout the PCIE protocol specification. Finally this study completes the RTL description,simulation and verification of PCIE data transmission system application layer, carriesout the analysis of the simulation results and tests the system practically. This articleincludes the following aspects:First of all, this article carries out in-depth studies about the PCIE protocol,alalyses the condition of PCIE native endpoint device implmention, selects thedevelopment platform, and then conducts the top-level design of PCIE datatransmission system and module division on the basis of in-depth understanding ofPCIE protocol.Secondly, this study configures the PCIE IP in Quartus II integrate developmentenvironment and introduces the interface of PCIE IP, and then employs Verilog HDL toRTL design of PCIE IP configuration module, support module of application layer, coremodule of application layer. The PCIE IP realizes function of PCIE protocol whichcommunicates with application layer through64bit Avalon-ST interface. PCIE IPconfiguration module realizes the sampling of PCIE IP configuration signals andconfiguration of PCIE error report capability register in configuration space throughLMI interface. The support module of application layer realizes receiving andtransmitting interface transformation, receiving interface buffer and MSI buffer. Thecore module of application layer realizes the data transmission function in Rc_slave andchaining DMA way. This article realizes the chaining DMA data transmission functionon the basis of DMA, reduces consumpustion of CPU resourcse, greattingly improvesthe efficiency of data transmission.Finally, it draws up simulation and tests for PCIE data transmission system. This article builds the testbench of system, which is used for function simulation of wholesystem. Compiles the whole design and uses the circuit been generated to configures theFPGA to verify the design time sequence. Run the test program on PC to test the systemin practical. Analyze the result of simulation and test.Through the thorough analysis of the simulation and test results of PCIE datatransmission system, it’s indicated that each module of IP core logic functions meetsrequirements of the design. System can exchange data with PC main memory inRc_slave and chaining DMA way, the DMA read speed archeives173MB/S and theDMA write speed archeives207MB/S.This design provides feasible and effectiveimplementations for PCIE data transmission using low cost FPGA, promotes the PCIEbus range of application and has good prospects.更多还原